Reviewing product and FW requirements Working with other ASIC architects and with system architects to define and document the feature sets and data/control flows implemented by the controller and each of its component IPs Defining requirements for ASIC design, verification, and physical implementation teams Evaluating area, performance, power, and ease-of-implementation trade-offs between different implementation solutions Reviewing and configuring 3rd party IPs Supporting other teams in the ASIC organization and reviewing their work Supporting product teams with documentation, code-reviews, and silicon debug Continuously finding opportunities for improving design quality and design practices Master's degree in Engineering Knowledge of RTL design in Verilog/SystemVerilog Knowledge in various aspects of SOC design, verification, and implementation flows Scripting and Unix shell language experience: e.g. Perl, Python, Unix shell scripts Ability to read and understand SW/FW code Understanding of CPU and memory architectures, data path pipelining mechanisms, distributed system design, ASIC low-power implementations, clock and reset methodologies Knowledge of PCIe + NVMe, CXL, and/or UFS in a storage application is preferred Experience with HW modeling languages ASIC architecture experience in storage products (e.g. SSD, eMMC, UFS, USB) Design/architecture experience with high-speed serial and parallel interfaces (e.g. PCIe, MIPI, DDR, LPDDR, ONFI) Design/architecture experience with NVMe, CXL, and/or UFS host protocols Familiarity with automotive design and qualification processes are a bonus
