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Chip Packaging Architect

Google • Full-time • Sunnyvale, CA, US • $192k - $278k / year • 6d ago

Minimum qualifications:

Bachelor's degree in Electrical/Computer Engineering, Computer Science, a related technical field, or equivalent practical experience.
10 years of experience in advanced packaging technology and high-volume production development.
Experience with optical sub-assemblies, including CPO, silicon photonics, VCSELs, and micro-LED integration.

Preferred qualifications:

Experience translating technical product requirements into packaging specifications.
Experience working within assembly houses or wafer foundries.
Knowledge of 2.5D/3D/3.5D heterogeneous integration (interposers, TSVs, RDL, micro-bumping, high-density substrates).
Understanding of end-to-end manufacturing flows, photonics fab processing, assembly processes, and reliability (component/board level).
Command of physical architecture, high-speed electrical/thermal performance, and thermo-mechanical constraints (warpage, materials).

About the job

Be part of a team that pushes boundaries, developing custom silicon solutions that power the future of Google's direct-to-consumer products. You'll contribute to the innovation behind products loved by millions worldwide. Your expertise will shape the next generation of hardware experiences, delivering unparalleled performance, efficiency, and integration.

As a Chip Packaging Architect on our Silicon Integration team, you will drive advanced packaging solutions (2.5D/3D/3.5D) and technologies for Machine Learning (ML) chips and custom Application-Specific Integrated Circuits (ASICs). You will collaborate with product architects, design teams, and Signal Integrity/Power Integrity (SI/PI), thermal, mechanical, assembly, and Printed Circuit Board (PCB) engineers to create high-performance packages. Your focus will span optical packaging technologies, design tradeoffs, assembly evaluation, mechanical reliability, and qualification, seeing systems through to high-volume manufacturing.

The US base salary range for this full-time position is $192,000-$278,000 + bonus + equity + benefits. Our salary ranges are determined by role, level, and location. Within the range, individual pay is determined by work location and additional factors, including job-related skills, experience, and relevant education or training. Your recruiter can share more about the specific salary range for your preferred location during the hiring process.

Please note that the compensation details listed in US role postings reflect the base salary only, and do not include bonus, equity, or benefits. Learn more about benefits at Google.

Responsibilities

Own product and packaging architecture for next-generation optical modules (e.g., CPO, uLED, VCSEL) and define manufacturing strategies for Tensor Processing Unit (TPU) packaging solutions.
Bridge hardware domains from silicon architects to platform teams, managing technical trade-offs across manufacturing, electrical, thermal, and mechanical parameters.
Drive advanced packaging concepts to high-volume manufacturing, proactively mitigating technical risks and authoring assembly processes and reliability test plans.
Lead cross-functional initiatives guiding new designs and test vehicles through qualification and New Product Introduction (NPI) phases.
Develop and scale the external supply chain vendor ecosystem while providing project management and clear communication across internal stakeholders and global suppliers.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also Google's EEO Policy and EEO is the Law. If you have a disability or special need that requires accommodation, please let us know by completing our Accommodations for Applicants form.